A typical prior art current mirror sense amplifier 20 is illustrated in FIG. 1. The amplifier 20 is formed using complementary metal oxide semiconductor (CMOS) field effect transistor (FET) technology. The amplifier 20 comprises two branches or circuits. A reference branch is formed by a P-channel transistor 22 connected in series with an N-channel transistor 24. An amplifying branch is formed by another P-channel transistor 26 and an N-channel transistor 28 connected in series. The sense amplifier 20 receives two input signals, one applied at a first input terminal 30 connected to the gate of input transistor 24 and the other applied at a second input terminal 32 connected to the gate of input transistor 28. An output signal from the amplifier 20 is supplied at an output terminal 34 which is connected to the junctions of the channels of transistors 26 and 28, which is also the branch output node of the amplifying branch. The junction of the channels of transistors 22 and 24 are commonly connected to the gates of the transistors 22 and 26 at a reference node 36, which is also the branch output node of the reference branch. The amplifier 20 shown in FIG. 1 is implemented in enhancement mode transistors, and therefore operates between a positive voltage source of power Vcc and a reference or more negative source of power Vss, supplied at first and second power terminals 38 and 40, respectively.
The input terminals 30 and 32 are normally biased at a level approximately midway between the levels of the power sources Vcc and Vss by means not shown (typically the preceding amplifier stages in a memory array integrated circuit). Under such input mid-level bias conditions, the reference branch transistors 22 and 24 are biased in a midpoint 41 of the vertical portion of a typical transfer curve 42 (FIG. 2) of a pair of complementary series connected transistors, such as transistors 22 and 24. The reference node 36 supplies a reference signal for biasing transistors 22 and 26 at the output voltage level of the reference branch transistors 22 and 24. With normal mid-level bias input signals at terminals 30 and 32, the output signal at terminal 34 is also located approximately at the midpoint 41 of the transfer curve 42, because the amplifying transistors 26 and 28 also function in accordance with the transfer curve 42 (FIG. 2).
The current mirror sense amplifier 20 operates in response to a differential input signal at the input terminals 30 and 32 and supplies a single ended output signal at the output terminal 34. First and second input signals are applied at terminals 30 and 32 respectively, and these input signals vary in mutually opposite directions with respect to the normal mid-level bias at these terminals. The first and second input signals define the differential input signal. The output signal at terminal 34 changes substantially from the midpoint on the transfer curve (FIG. 2) due to much smaller relative changes in the magnitude of the input signals. The amount of change in the output signal is the amplified difference between the two input signals, and the level which the output signal assumes is dependent on the relative levels of the input signals, as is illustrated by the following description of operation of the sense amplifier 20.
Assume a positive increase in the input signal applied at terminal 30 and a corresponding decrease in the input signal applied at terminal 32, relative to their normal mid-level bias magnitudes. Transistor 24 becomes more conductive, lowering the reference signal level at the reference node 36 and increasing the conductivity of the transistor 22. A similar effect occurs on transistor 26, and it too becomes more conductive. The decrease in input signal to transistor 28 decreases its conductivity. The increased conductivity of transistor 26 and the decreased conductivity of transistor 28 raise the level of the output signal at the output terminal 34. Thus, a relative increase in the input signal at terminal 30 and a relative decrease in the input signal at terminal 32 cause an increase in the level of the output signal at terminal 34. If the input signal differential is substantial enough, the level of the output signal at terminal 34 will attain a level approximating that of Vcc.
Conversely, an increase in the input signal at terminal 32 and a decrease in the input signal at terminal 30 causes transistor 24 to become less conductive, thereby raising the reference signal level at the reference node 36 and decreasing the conductivity of transistors 22 and 26. The increased signal at terminal 32 causes transistor 28 to become more conductive. The more conductive transistor 28 and the less conductive transistor 26 cause the level of the output signal at the terminal 34 to decrease. Thus, a relative decrease in the input signal at terminal 30 and a relative increase in the input signal at terminal 32 cause a decrease in the level of the output signal at terminal 34. If the input signal differential is substantial enough, the level of the output signal at terminal 34 will attain a level approximating that of Vss.
The amplifier 20 is referred to as a current mirror because, as can be understood from the previous explanation, the change in current flowing through one branch corresponds to or is "mirrored+ with the change in current in the other branch. The mirror effect occurs because the transistors 22 and 26 control the amount of current flowing through both branches, and both transistors 22 and 26 are comparably or equally affected by the changes in the bias reference signal at reference node 36.
An important point to note with respect to the prior art amplifier 20 is that an active current will always flow through and be dissipated by the reference branch transistors 22 and 24, except in the one case where the input signal applied to terminal 30 is at the level of Vss, which terminates the conduction of transistor 24. Rarely, however, will an input signal situation exist where the reference branch does not consume current, because the input signals usually do not approach the levels of Vcc and Vss, and then if the input signals do approach the levels of Vcc and Vss, there is only one active state where the reference branch does not consume current.
The vast majority of applications for a current mirror sense amplifier are as a later stage amplifier, to supply either a high logical signal (approaching Vcc) or a low logical signal (approaching Vss) from two differentially-related output signals representative of a single logical state of an addressed memory cell of a memory array. One such application is in SRAM (static random access memory) cells, where the output signal must be held for a considerable length of time. While supplying the output signal, the reference branch consumes or dissipates current. The current consumed during these conditions generates undesirable heat and reduces the amount of power available for other circuit components.
Another concern applicable to a current mirror sense amplifier is the level of the output signal. The output signal level should clearly establish one logical state or the other, in response to a reasonable input signal differential and for a reasonable number of circuit components which form the load for the sense amplifier. If the level of the output signal is insufficient, another sense amplifier or an additional stage of amplification will be required to obtain the desired signal level. Of course additional amplifying stages consume additional space in the integrated circuit and require the fabrication of additional components. Accordingly, it is desirable to maximize the output signal level from the sense amplifier.
It is against this background information pertaining to prior art current mirror sense amplifiers, and the considerations related to current consumption and maximizing the output signal changes, that the present invention has evolved.